Thin film transistors (hereafter, simply referred to as TFT sometimes in this specification) are devices that can be formed over an insulator substrate of glass or the like and undertake an important role in electronic technology. Amorphous silicon or polycrystalline silicon is presently most widely used as a channel layer material of TFTs. In recent years, however, metal oxide semiconductors have come under the spotlight as a channel layer material of TFTs in an attempt to replace these silicon materials. In addition to its excellent characteristics for channel layers, the metal oxide semiconductor is characterized in that it can be formed at near room temperature. For this reason, it is considered as one of major candidates of a channel layer material when TFT is formed over a so-called flexible substrate such as a plastic film.
However, the oxide semiconductor has a disadvantage. When exposed to plasma or accelerated particles, it is damaged (oxygen defect) and is reduced in resistance and may be turned conductive sometimes. For this reason, it is required to deal with the two challenges described below to form a top-contact TFT with the same structure as that of amorphous silicon TFTs presently in wide use in industry. First, it is required to eliminate damage an oxide semiconductor suffers when a metal film is formed over the oxide semiconductor by a method, such as sputtering, involving the production of plasma or accelerated particles. Second, it is required to eliminate damage an oxide semiconductor suffers when dry etching is adopted to process a metal film to form a source/drain electrode. The formation of a metal film by sputtering is high in mass productivity and is in wide use in industry because of excellence in resulting film quality, film formation speed, uniformity, and yield. The dry etching process is also excellent in processing accuracy and processing speed and is high in mass productivity and in wide use in industry.
Methods for dealing with the above two challenges are reported in Non-patent Documents 1 (Electrochemical and Solid-State Letters, 12 (4) H95-H97 (2009)) and 2 (Journal of The Electrochemical Society, 156 (3) H184-H187 (2009)). In the method in Non-patent Document 1, a region 30 nm or so in thickness, damaged by dry etching, in an In—Ga—Zn—O channel layer is removed by wet etching. In the method in Non-patent Document 2, an etch stopper layer is formed of Cu—In—Ga—Zn—O (high-resistance semiconductor) over an In—Ga—Zn—O channel layer to absorb damage caused during dry etching of a source/drain electrode.